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このアイテムの引用には次の識別子を使用してください: http://hdl.handle.net/10445/5738

タイトル: Vision Chip Architecture for Detecting Line of Sight Including Saccade
著者: Akita, J.
Takagi, H.
Nagasaki, Takeshi
Toda, Masashi
Kawashima, Toshio
Kitagawa, A.
アブストラクト: Rapid eye motion, or so called saccade, is a very quick eye motion which always occurs regardless of our intention. Although the line of sight (LOS) with saccade tracking is expected to be used for a new type of computer-human interface, it is impossible to track it using the conventional video camera, because of its speed which is often up to 600 degrees per second. Vision Chip is an intelligent image sensor which has the photo receptor and the image processing circuitry on a single chip, which can process the acquired image information by keeping its spatial parallelism. It has also the ability of implementing the very compact integrated vision system. In this paper, we describe the vision chip architecture which has the capability of detecting the line of sight from infrared eye image, with the processing speed supporting the saccade tracking. The vision chip described here has the pixel parallel processing architecture, with the node automata for each pixel as image processing. The acquired image is digitized to two flags indicating the Purkinje's image and the pupil by comparators at first. The digitized images are then shrunk, followed by several steps of expanding by node automata located at each pixel. The shrinking process is kept executed until all the pixels disappear, and the pixel disappearing at last indicates the center of the Purkinje's image and the pupil. This disappearing step is detected by the projection circuitry in pixel circuit for fast operation, and the coordinates of the center of the Purkinje's image and the pupil are generated by the simple encoders. We describe the whole architecture of this vision chip, as well as the pixel architecture. We also describe the evaluation of proposed algorithm with numerical simulation, as well as processing speed using FPGA, and improvement in resolution using column parallel architecture.
研究業績種別: 原著論文/Original Paper
資料種別: Journal Article
査読有無: あり/yes
単著共著: 共著/joint
発表雑誌名,発表学会名など: IEICE Transactions on Electronics
巻: E89-C
号: 11
開始ページ: 1605
終了ページ: 1611
年月日: 2006年11月1日
出版社: 電子情報通信学会
出現コレクション:川嶋 稔夫


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