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このアイテムの引用には次の識別子を使用してください: http://hdl.handle.net/10445/5726

タイトル: Column-Parallel Vision Chip Architecture for High-Resolution Line-of-Sight Detection Including Saccade
著者: Akita, Junichi
Takagi, Hiroaki
Doumae, Keisuke
Kitagawa, Akio
Toda, Masashi
Nagasaki, Takeshi
Kawashima, Toshio
アブストラクト: Although the line-of-sight (LoS) is expected to be useful as input methodology for computer systems, the application area of the conventional LoS detection system composed of video camera and image processor is restricted in the specialized area, such as academic research, due to its large size and high cost. There is a rapid eye motion, so called 'saccade' in our eye motion, which is expected to be useful for various applications. Because of the saccade's very high speed, it is impossible to track the saccade without using high speed camera. The authors have been proposing the high speed vision chip for LoS detection including saccade based on the pixel parallel processing architecture, however, its resolution is very low for the large size of its pixel. In this paper, we propose and discuss an architecture of the vision chip for LoS detection including saccade based on column-parallel processing manner for increasing the resolution with keeping high processing speed.
研究業績種別: 原著論文/Original Paper
資料種別: Journal Article
査読有無: あり/yes
単著共著: 共著/joint
発表雑誌名,発表学会名など: IEICE Trans. on Electronics
巻: E90-C
号: 10
開始ページ: 1869
終了ページ: 1875
年月日: 2007年10月1日
出版社: 電子情報通信学会
出現コレクション:川嶋 稔夫

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